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      Seokmin.Lee

      Hello, I am a master's student in the Department of Convergence Security (Samsung Advanced Security) at Korea University.After graduation, I am expected as a security developer or researcher member of Samsung SDS.

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[paper]meltdown:reading kernel memory from userspace

24 Dec 2020

Abstract

Introduction

Background

Out of oreder excution

  • In practice, CPUs supporting out-of-order execution allow running operations speculatively to the extent that the processorโ€™s out-of-order logic processess instructions before the CPU is certain that the instruction will be needed and committed.
  • In this paper, we refer to speculative execution in a more restricted meaning, where it refers to an instruction sequence following a branch, and use the term out of order execution to refer to any way of getting an operation executed before the processor has committed the results of all prior instructions.
  • For dynamic scheduling of instructions to allow out-of-order execution
    • A unified reservation station allows a CPU to use a data value as it has been computed instead of sorting it in a register and re-reading it.
    • The reservation station renames registers to allow instructions that operate on the same physical registers to use the last logical one to solve read-after-write, WAR, WAW hazards

      MULTD F4,F2,F2
      ADDD F2,F0,F6(X)
      ADDD F8,F0,F6(Dependency on F2 donโ€™t occur)

  • ์Šˆํผ ์Šค์นผ๋ผ์™€ ๊ฐ™์ด CPU ๋‚ด์— ํŒŒ์ดํ”„ ๋ผ์ธ์— 4๊ฐœ์—์„œ~5๊ฐœ ๋˜๋Š” ๋ช…๋ น์–ด๋“ค์ด ๊ฐ™์ด ํŒจ์น˜ ๋˜๊ฒŒ๋œ๋‹ค.
    • ๊ทธ๋ฆฌ๊ณ  ๊ทธ ๋ช…๋ น์–ด๋“ค์€ ๋งˆ์ดํฌ๋กœ์˜ต์Šค์— ์˜ํ•ด ๋””์ฝ”๋”ฉ ๋˜์–ด์ง€๊ณ  Reorder Buffer๋กœ ๋ณต์‚ฌ๊ฐ€ ๋˜์–ด์ง„๋‹ค.
  • ์ด๋•Œ Reorder Buffer์—์„œ ์˜์กด์„ฑ์ด ์žˆ๋Š” ๋ ˆ์ง€์Šคํ„ฐ๋“ค์„ renaming ํ•ด์ฃผ๋Š” ๋“ฑ์˜ ๊ณผ์ •์„ ์ง„ํ–‰ํ•ด์ฃผ์–ด in-order์—์„œ out-of-order๋กœ ์ตœ์ ํ™”๋œ ๋ช…๋ น์–ด ์ˆ˜ํ–‰์ด ๋œ๋‹ค. ๊ทธ๋ฆฌ๊ณ  queue(Unified Reservation Station)์— ๋“ค์–ด๊ฐ€๊ฒŒ ๋ ๋•Œ ์›๋ž˜์˜ ์ˆœ์„œ์— ๋งž๊ฒŒ ์ •๋ ฌ์ด ๋˜์–ด์ง„๋‹ค.

Speculative excution

  • ์ด๋Š” out-of-order์™€ ๋‹ค๋ฅธ excution์ด๋‹ค.

    IF( CONDITION ){ } ELSE { }

์—์„œ, ์ถ”์ธก์‹คํ–‰์ด๋ž€ CONDITION์ด ๋งž๋‹ค๋Š” ๊ฐ€์ •ํ•˜์— CONDITION์•ˆ์˜ BODY๋ฅผ ์‹คํ–‰์‹œํ‚ค๋Š” ๋ช…๋ น์–ด์ด๋‹ค.

  • Out of order excution๊ณผ ๊ตฌ๋ถ„์ด ํ•„์š”ํ•˜๋‹ค.

Cache Attacks

A Toy Example

raise_exception();
access(probe_array[data * 4096])

  • ์ด ๊ณผ์ •์—์„œ ์ง‘์ค‘ํ•ด์•ผํ•˜๋Š” ๊ฒƒ์€ data์˜ * 4096๋ฒˆ์ง€๋ฅผ ๊ณฑํ•œ ๊ฒƒ์ด๋‹ค. ๊ทธ ์ด์œ ๋Š” flush+reload์—์„œ ์•„์ด๋””์–ด๋ฅผ ์–ป์„ ์ˆ˜ ์žˆ๋Š” ๊ฒƒ๊ณผ ๋งˆ์ฐฌ๊ฐ€์ง€๋กœ, prefetch๋•Œ๋ฌธ์ด๋‹ค. flush+reload์—์„œ ๋กœ๋“œํ•˜๋Š” ๊ณผ์ •์—์„œ ํŽ˜์ด์ง€ ๋‹จ์œ„๋กœ ๋กœ๋“œ๋ฅผ ํ•˜๊ธฐ ๋•Œ๋ฌธ์— ์ •ํ™•ํžˆ ์–ด๋А ๊ณณ์˜ ์ ‘๊ทผ์„ ํ–ˆ๋Š”์ง€์— ๋Œ€ํ•ด์„œ ํŒŒ์•…ํ•  ์ˆ˜ ์—†๋‹ค. ๊ทธ๋ ‡๊ธฐ์— ๊ทธ๊ฒƒ์„ ๋ง‰์•„์ฃผ๊ณ ์ž data์— 4096์„ ๊ณฑํ•˜์—ฌ ์›ํ•˜๋Š” ์ปค๋„ ์ฃผ์†Œ(๋ฐ์ดํ„ฐ)์˜ ๊ฐ’์„ ํŒŒ์•…ํ•˜๊ธฐ ์šฉ์ดํ•˜๊ฒŒ ๋งŒ๋“ค ์ˆ˜ ์žˆ๋‹ค.
  • ์ฒซ๋ฒˆ์งธ ๋ผ์ธ์—์„œ ์›๋ž˜๋Œ€๋กœ๋ผ๋ฉด EXCEPTION์ด ๋ฐœ๋™๋˜์–ด, ๋‘๋ฒˆ์งธ ๋ช…๋ น์–ด๊ฐ€ ์‹คํ–‰์ด ๋˜๋ฉด ์•ˆ๋œ๋‹ค.
  • ํ•˜์ง€๋งŒ ์Šˆํผ์Šค์นผ๋ผ์— ์˜ํ•ด์„œ ๋‘๊ฐ€์ง€์˜ ๋ช…๋ น์–ด๊ฐ€ ๊ฐ™์ด ํŽ˜์น˜๋˜์–ด, Reorder Buffer์—์„œ ๋‘๊ฐœ์˜ ๋ช…๋ น์–ด๋‹ค ์‹คํ–‰์ด ๊ฐ€๋Šฅํ•œ ์ƒํƒœ๋กœ ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ์„ ํ•œ๋‹ค.
  • ๊ทธ๋ ‡๊ฒŒ ๋˜๋ฉด ์ด๋ฏธ ์ ‘๊ทผํ•œ ๋ฉ”๋ชจ๋ฆฌ์— ๋Œ€ํ•œ ํŽ˜์ด์ง€๋“ค์ด ์บ์‹œ์— ์˜ฌ๋ผ์™€์žˆ๊ฒŒ ๋˜๊ณ , ์‹คํ–‰๋œ probe_array์˜ ๋ชจ๋“  ํŽ˜์ด์ง€๋“ค์„ Flush+Reload๋ฅผ ์ง„ํ–‰ํ•˜๊ฒŒ๋˜๋ฉด data์— ํŠน์ • ํŽ˜์ด์ง€์— ๋Œ€ํ•œ ์ ‘๊ทผ๋งŒ ๋น ๋ฅด๊ฒŒ ๋จ์œผ๋กœ ์–ด๋А ํŽ˜์ด์ง€๊ฐ€ ๋ฌผ๋ฆฌ ๋ฉ”๋ชจ๋ฆฌ์— ์ ‘๊ทผ ๋˜์—ˆ๋Š”์ง€๋ฅผ ํ™•์ธํ•  ์ˆ˜ ์žˆ๊ฒŒ๋œ๋‹ค.
  • access์™€ ๊ฐ™์ด ์ผ์‹œ์ ์œผ๋กœ ์กด์žฌ๋˜๋Š” ๋ช…๋ น์–ด๋“ค์„ transient instruction์ด๋ผ ๋ถ€๋ฅธ๋‹ค.
  • ๋น„๋ฐ€ ๊ฐ’์„ ์œ ์ถœ์‹œํ‚ค๊ธฐ ์œ„ํ•ด์„œ๋Š” transient instruction์ด ๊ณต๊ฒฉ์ž๊ฐ€ ์œ ์ถœ์‹œํ‚ค๊ธฐ ์›ํ•˜๋Š” ๋น„๋ฐ€ ๊ฐ’์„ ์ด์šฉํ•˜๊ณ  ์žˆ์–ด์•ผ๋งŒํ•œ๋‹ค.

Building Blocks of the Attack

meltdown_block

  • Meltdown ๊ตฌํ˜„์˜ ์ฒซ๋ฒˆ์งธ block์—์„œ๋Š” transient instruction์˜ ์‹คํ–‰์ด ์žˆ๊ณ , CPU๊ฐ€ ๊ฒฝํ—˜์  ์ง€์†์‹œ๊ฐ„์„ ์ตœ์ ํ™” ์‹œํ‚ค๊ธฐ์œ„ํ•ด์„œ ๊ณ„์†์ ์œผ๋กœ ํ˜„์žฌ ๋ช…๋ น์–ด ์•ž์—์„œ ์‹คํ–‰๋˜๊ณ  ์žˆ๊ธฐ ๋–„๋ฌธ์— ๋ชจ๋“  ์ˆœ๊ฐ„์— ์ผ์–ด๋‚œ๋‹ค.
  • Transient Instuction์€ ๋งŒ์•ฝ ๊ทธ๋“ค์˜ operation์ด secret value๋ฅผ ๊ฐ–๊ณ  ์žˆ๋‹ค๋ฉด side channel attack์„ ์‹คํ–‰์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค.
  • userspace์—์„œ kernel space๋ฅผ ์ ‘๊ทผํ•˜๋Š” ์ฃผ์†Œ๊ฐ’์ด์—ฌ์•ผ ํ•˜๊ณ , kernel space์ธ ์ด์œ ๋Š” kernel address space์—์„œ๋Š” ๋ชจ๋“  physical memory๋กœ์˜ ์ ‘๊ทผ์ด ๊ฐ€๋Šฅํ•˜๊ธฐ ๋–„๋ฌธ์ด๋‹ค.
  • ํ•˜์ง€๋งŒ userspace์—์„œ kernelspace๋ฅผ ์ ‘๊ทผํ•˜๋Š” ๊ฒƒ์€ ์˜ˆ์™ธ์ฒ˜๋ฆฌ๋ฅผ ๋ฐœ์ƒ์‹œํ‚ค๊ณ  ๋ฐ”๋กœ ์–ดํ”Œ๋ฆฌ์ผ€์ด์…˜์ด ์ข…๋ฃŒ๋˜๋„๋ก ๋งŒ๋“ค์–ด๋ฒ„๋ฆฐ๋‹ค. ๊ทธ๋ ‡๊ธฐ์— ์˜ˆ์™ธ์ฒ˜๋ฆฌ๊ฐ€ ๋ฐœ์ƒ๋˜๋”๋ผ๋„ ๊ทธ๊ฒƒ์„ ๋‹ค๋ฃฐ ์ˆ˜ ์žˆ๋Š” ๊ณผ์ •์ด ์žˆ์–ด์•ผ๋งŒ ๊ณต๊ฒฉ์ž๋Š” Secret value๋ฅผ ๋ˆ„์ถœ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค.

Excuting Transient Instructions

  • ์›๋ž˜๋Œ€๋กœ๋ผ๋ฉด exception์ด ๋ฐœ๋™๋˜์—ˆ์„๋•Œ ๋ฐ”๋กœ ๊บผ์ ธ์•ผ ํ•˜๋Š”๋ฐ ๋ฐ”๋กœ ๊บผ์ง€์ง€ ์•Š๊ฒŒ ์–ด๋–ป๊ฒŒ ํ• ๊นŒ?
    1. Exception handling: ์˜ˆ์™ธ์ฒ˜๋ฆฌ๊ฐ€ ์ผ์–ด๋‚œ ํ›„๋ฅผ ํšจ๊ณผ์ ์œผ๋กœ ๋‹ค๋ฃจ๋Š” ๋ฐฉ๋ฒ•
  • ์œ ํšจํ•˜์ง€ ์•Š๋Š” ๋ฉ”๋ชจ๋ฆฌ ์ฃผ์†Œ๊ฐ’์„ ์ ‘๊ทผํ•˜๊ธฐ ์ „์— ๊ณต๊ฒฉํ•˜๋Š” ์ค‘์ธ application์„ forkํ•˜๋Š” ๋ฐฉ๋ฒ•์ด๋‹ค. ๊ทธ๋ฆฌ๊ณ  child process์—์„œ๋งŒ ์œ ํšจํ•˜์ง€ ์•Š๋Š” ๋ฉ”๋ชจ๋ฆฌ ์œ„์น˜๋กœ ์ ‘๊ทผํ•˜๋Š” ๊ฒƒ์ด๋‹ค.
    • CPU๋Š” transient instuction sequence๋ฅผ child process์—์„œ ์ถฉ๋Œ๋‚˜๊ธฐ์ „์— ์‹คํ–‰ํ•œ๋‹ค.
    • Parent Porcess๋Š” Microarchitectural state(side-channel)๋ฅผ ๊ด€์ฐฐํ•จ์œผ๋กœ์จ secret value๋“ค์„ ๋ณต๊ตฌํ•  ์ˆ˜ ์žˆ๋‹ค.
  • ํŠน์ •ํ•œ ์˜ˆ์™ธ์ฒ˜๋ฆฌ๊ฐ€ ์ผ์–ด๋‚ฌ์„ ๋•Œ ์‹œํ–‰๋˜๋Š” Signal handler๋ฅผ ์„ค์น˜ํ•˜๋Š” ๊ฒƒ์œผ๋กœ๋„ ๊ฐ€๋Šฅํ•˜๋‹ค.
    • ๊ณต๊ฒฉ์ž๊ฐ€ ๋ช…๋ น์–ด๋“ค์˜ sequence๋ฅผ ๋ฐœํ–‰ํ•˜๋„๋ก ํ•˜๊ณ , ๊ทธ๋ฆฌ๊ณ  crash๋กœ๋ถ€ํ„ฐ ์–ดํ”Œ๋ฆฌ์ผ€์ด์…˜์„ ๋ง‰์Œ์œผ๋กœ์จ ์ƒˆ๋กœ์šด ํ”„๋กœ์„ธ์Šค๋ฅผ ์ƒ์„ฑํ•˜์ง€ ์•Š๊ธฐ ๋•Œ๋ฌธ์— overhead๋ฅผ ์ค„์ผ ์ˆ˜ ์žˆ๋‹ค. 2. Exception suppression: ์˜ˆ์™ธ์ฒ˜๋ฆฌ๊ฐ€ ์ผ์–ด๋‚˜๋Š” ๊ฒƒ์„ ๋ง‰๊ณ  ๊ทธ๋ฆฌ๊ณ  control flow๋ฅผ redirectํ•˜๋Š” ๋ฐฉ๋ฒ•
  • ์ฒ˜์Œ ๋ฌธ์ œ๊ฐ€ ์ œ๊ธฐ๋˜๋Š” ๊ฒƒ์—์„œ๋ถ€ํ„ฐ ์˜ˆ์™ธ์ฒ˜๋ฆฌ ํ›„ ๊บผ์ง€๋Š” ๊ฒƒ์„ ๋ง‰์•„๋ฒ„๋ฆฌ๋Š” ๋ฐฉ๋ฒ•
  • Transaction memory๋Š” ๋ฉ”๋ชจ๋ฆฌ Access๋ฅผ ํ•˜๋‚˜์˜ ์›์ž ์ž‘๋™์œผ๋กœ ์‚ฌ์šฉํ•  ์ˆ˜ ์žˆ๊ฒŒ ๊ทธ๋ฃนํ™” ํ•ด์ฃผ์–ด, ์—๋Ÿฌ๊ฐ€ ๋ฐœ์ƒํ•œ๋‹ค๋ฉด ๊ทธ ์ด์ „์˜ ์ƒํƒœ๋กœ ๋Œ์•„๊ฐˆ ์ˆ˜ ์žˆ๋„๋ก option์„ ์ œ๊ณตํ•ด์ค€๋‹ค.
  • ๋งŒ์•ฝ ์˜ˆ์™ธ์ฒ˜๋ฆฌ๊ฐ€ Transaction์—์„œ ๋ฐœ์ƒ๋œ๋‹ค๋ฉด, architectural state๋Š” ์ดˆ๊ธฐํ™”๋˜๊ณ , ๊ทธ๋ฆฌ๊ณ  ํ”„๋กœ๊ทธ๋žจ ์‹คํ–‰์€ ๋ฐฉํ•ด์—†์ด ์ง€์†๋œ๋‹ค.
  • Speculative execution์€ branch misprediction๋•Œ๋ฌธ์— ์‹คํ–‰๋œ ์ฝ”๋“œ path์—์„œ ์‹คํ–‰๋˜์ง€ ์•Š์„ ๊ฒƒ ๊ฐ™์€ ๋ช…๋ น์–ด๋ฅผ ๋ฐœ์ƒ์‹œํ‚จ๋‹ค.
  • ์ด์ „ ์กฐ๊ฑด branch๋ฅผ ์ฒ˜๋ฆฌํ•˜๋Š” ๊ฒƒ์— ๋”ฐ๋ฅด๋Š” ์ด๋Ÿฌํ•œ ๋ช…๋ น์–ด๋“ค์€ ์ถ”์ธก์ ์œผ๋กœ ์‹คํ–‰๋œ๋‹ค.
  • ๊ทธ๋Ÿผ์œผ๋กœ, ์œ ํšจํ•˜์ง€ ์•Š์€ ๋ฉ”๋ชจ๋ฆฌ์˜ ์ ‘๊ทผ์€ (๋‹จ์ง€ ์ด์ „์˜ branch condition์ด true์ด๊ธฐ์— ์‹คํ–‰์ด ๋˜์—ˆ๋˜) ์ถ”์ธก๋ช…๋ น์–ด๋“ค์— ์˜ํ•ด์„œ ์‹คํ–‰๋˜์–ด์ง„๋‹ค.
  • condition๋“ค์ด ์‹คํ–‰ ์ฝ”๋“œ์—์„œ ๊ฒฐ์ฝ” true๋ผ๊ณ  ํ‰๊ฐ€ํ•˜์ง€ ์•Š์„ ๊ฒƒ์ด๋ผ ํ™•์‹ ์ด๋“ค๋„๋ก ๋งŒ๋“ฆ์œผ๋กœ์จ ์šฐ๋ฆฌ๋Š” ์ผ์–ด๋‚˜๋Š” ์˜ˆ์™ธ๋“ค(๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ์ด ๋‹จ์ง€ ์ถ”์ธก์ ์ด๊ฒŒ ์‹คํ–‰๋˜์–ด์ง€๋Š”)์„ ์–ต์••์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค.

Building a Covert Channel

  • ๋‘๋ฒˆ์งธ Meltdown block์„ ๋ณด๊ฒŒ๋˜๋ฉด transient instruction์ด ๋งˆ์ง๋ง‰์—๋Š” microarchitectual covert channel์„ ํ†ตํ•ด ์ •๋ณด๋ฅผ ๋ณด๋‚ด๊ณ  ์žˆ๋Š” ๊ฒƒ์„ ํ™•์ธํ•  ์ˆ˜ ์žˆ๋‹ค.
  • covert channel์˜ ๋์—์„œ ๋ฐ›๋Š” ๊ฒƒ์€ microarchitectural์˜ ๋ณ€ํ™”๋ฅผ ๋ฐ›๋Š” ๊ฒƒ์ด๊ณ  state๋กœ๋ถ€ํ„ฐ secret์„ ์ถ”์ •ํ•  ์ˆ˜ ์žˆ๊ฒŒ ํ•˜๋Š” ๊ฒƒ์ด๋‹ค.
  • ๋ฐ›๋Š” ๊ณณ์€ transient sequence์˜ ๋ถ€๋ถ„์ด ์•„๋‹˜์„ ์ฃผ๋ชฉํ•˜๊ณ  ๋‹ค๋ฅธ ์“ฐ๋ ˆ๋“œ, ๋˜๋Š” ํ”„๋กœ์„ธ์Šค๊ฐ€ ๋  ์ˆ˜ ์žˆ๋‹ค. (์˜ˆ๋ฅผ๋“ค์–ด fork์—์„œ parents process)
  • ์šฐ๋ฆฌ๋“ค์€ Cache attack์œผ๋กœ๋ถ€ํ„ฐ ๊ธฐ์ˆ ๋“ค์„ ์˜ํ–ฅ๋ ฅ์žˆ๊ฒŒ ํ•œ๋‹ค. ์™œ๋ƒํ•˜๋ฉด cache state๋Š” ๋‹ค์–‘ํ•œ ๊ธฐ์ˆ ๋“ค์„ ์‚ฌ์šฉํ•ด์„œ architectual state๋ฅผ ๋ฏฟ์„ ์ˆ˜ ์žˆ๊ฒŒ ์ „์†ก๋˜์–ด์งˆ ์ˆ˜ ์žˆ๋Š” microarchitectural state์ด๊ธฐ ๋•Œ๋ฌธ์ด๋‹ค.
  • ํŠนํžˆ ์šฐ๋ฆฌ๋Š” F+R์„ ์‚ฌ์šฉํ•˜๊ณ , secret value์— ๋”ฐ๋ผ์„œ transient instruction sequence๋Š” regular memory access๋ฅผ ์‹œํ–‰ํ•œ๋‹ค.
  • trasient instruction sequence๊ฐ€ ์ ‘๊ทผํ•  ์ˆ˜ ์žˆ๋Š” ํŽ˜์ด์ง€์— ์ ‘๊ทผํ•œ ํ›„์—(covert channel์˜ sender์˜ ์‹คํ–‰ํ•œ ํ›„์—), ์ฃผ์†Œ๋Š” subsequent access๋ฅผ ์œ„ํ•ด cached ๋˜์–ด์ ธ์žˆ๋‹ค.
  • receiver๋Š” ์ด๊ฒƒ์„ ๊ฐ์‹œํ•  ์ˆ˜ ์žˆ๋‹ค. ์ฃผ์†Œ๊ฐ€ cache์— load๋˜์—ˆ๋Š”์ง€ ์•ˆ๋˜์—ˆ๋Š”์ง€๋ฅผ, ์ฃผ์†Œ์˜ access time์„ ์ธก์ •ํ•จ์œผ๋กœ์จ(FR์˜ ๊ฐœ๋…)
  • ๊ทธ๋Ÿผ์œผ๋กœ sender๋Š” ์ฃผ์†Œ์— ์ ‘๊ทผํ•จ์œผ๋กœ์จ 1์„ ๋ณด๋‚ผ ์ˆ˜ ์žˆ๊ณ  ์ฃผ์†Œ์— ์ ‘๊ทผํ•˜์ง€ ์•Š์Œ์œผ๋กœ์จ 0์„ ๋ณด๋‚ผ ์ˆ˜ ์žˆ๋‹ค.
  • in toy example
    • ๋‹ค์ˆ˜์˜ ๋‹ค์–‘ํ•œ ์ข…๋ฅ˜์˜ cache line๋“ค์„ ์‚ฌ์šฉํ•จ์œผ๋กœ์จ ํ•œ๋ฒˆ์— multibit์„ ์ „์†กํ•  ์ˆ˜ ์žˆ๋‹ค.
    • ๋ชจ๋“  256 different byte value๋ฅผ ์œ„ํ•ด sender๋Š” ๋‹ค๋ฅธ cache line์„ ์ ‘๊ทผํ•  ์ˆ˜ ์žˆ๋‹ค.
    • 256 ๊ฐ€๋Šฅํ•œ ๋ชจ๋“  cache๋ผ์ธ๋“ค์— Flush+Reload ๊ณต๊ฒฉ์„ ์ง„ํ–‰ํ•จ์œผ๋กœ์จ receiver๋Š” ํ•œ๋น„ํŠธ๊ฐ€ ์•„๋‹Œ ๋ชจ๋“  ๋น„ํŠธ๋ฅผ ๋ณต๊ตฌํ•  ์ˆ˜ ์žˆ๋‹ค.
    • ํ•˜์ง€๋งŒ F+R ๊ณต๊ฒฉ์€ ๋งค์šฐ ๊ธธ๊ธฐ ๋•Œ๋ฌธ์—, ํ•œ๋ฒˆ์— ํ•œ๋น„ํŠธ๋งŒ ๋ณด๋‚ด๋Š” ๊ฒƒ์ด ๋” ํšจ๊ณผ์ ์ด๋‹ค.
    • ๊ณต๊ฒฉ์ž๋Š” ๊ฐ„๋‹จํ•˜๊ฒŒ secret value๋ฅผ ๋ณ€์กฐํ•˜๊ณ  ๋ณ€ํ™” ์‹œํ‚ฌ ์ˆ˜ ์žˆ๋‹ค.
  • ๋‹ค๋ฅธ instruction์„ ๊ฐ–๊ณ  covert channel ๋งŒ๋“ค๊ธฐ
    • covert channel์€ ๋‹จ์ง€ cache์— ์˜์กด๋˜์–ด์ง„ microachitectural์— ์ œํ•œ๋˜์–ด ์žˆ์ง€์•Š๋‹ค.
    • ๋ชจ๋“  mircroarchitectual state๋Š” instruction์—์˜ํ•ด ์˜ํ–ฅ๋ฐ›์•„์งˆ ์ˆ˜ ์žˆ๊ณ  side channel(covert channel์„ ๋งŒ๋“ค ์ˆ˜ ์žˆ๋Š”)์„ ํ†ตํ•ด ๊ด€์ธก๋˜์–ด์งˆ ์ˆ˜ ์žˆ๋‹ค.
    • ์˜ˆ๋ฅผ๋“ค์–ด 1bit์„ ๋ณด๋‚ด๊ธฐ ์œ„ํ•ด์„œ ALU์™€ ๊ฐ™์€ ์‹คํ–‰ port(?)๋ฅผ ์ ๋ นํ•จ์œผ๋กœ์จ covert channel์„ ๋งŒ๋“ค ์ˆ˜ ์žˆ๋‹ค.
    • receiver๋Š” ๊ฐ™์€ ๋ช…๋ น์–ด port์—์„œ instruction์„ ์‹คํ–‰ํ•  ๋•Œ latency๋ฅผ ์ธก์ •ํ•  ์ˆ˜ ์žˆ๋‹ค. ๋†’์€ latency๋Š” 1bit๋ฅผ sender๊ฐ€ ๋ณด๋ƒˆ์Œ์„ ๋งํ•ด์ฃผ๊ณ , ๋‚ฎ์€ latency๋Š” 0์„ ๋ณด๋ƒˆ์Œ์„ ์•Œ ์ˆ˜ ์žˆ๋‹ค.
    • ๊ทธ๋Ÿผ์œผ๋กœ F+R์˜ ์žฅ์ ์€ ๋…ธ์ด์ฆˆ๊ฐ€ ์ ๊ณ  ๋†’์€ ์ „๋‹ฌ์„ฑ์„ ๊ฐ–๊ณ  ์žˆ๋‹ค.
    • ๋ชจ๋“  cpu์ฝ”์–ด๋กœ ๋ถ€ํ„ฐ ๋ˆ„์ˆ˜๋“ค์„ ๊ด€์ธกํ•  ์ˆ˜ ์žˆ๋‹ค.

Meltdown

1 ; rcx = kernel address, rbx = probe array
2 xor rax, rax
3 retry:
4 mov al, byte [rcx]
5 shl rax, 0xc
6 jz retry
7 mov rbx, qword [rbx + rax]

  • ์ด๋ฒˆ ์žฅ์—์„œ๋Š” ๊ถŒํ•œ์ด ์—†๋Š” user program์—์„œ ์ž„์˜์˜ ๋ฌผ๋ฆฌ ๋ฉ”๋ชจ๋ฆฌ๋ฅผ ์ฝ๋Š” ๊ฐ•๋ ฅํ•œ ๊ณต๊ฒฉ์ธ meltdown์„ ์†Œ๊ฐœํ•œ๋‹ค.
    1. ์ฒซ๋ฒˆ์งธ๋กœ ์ด ๊ณต๊ฒฉ์˜ ๋„“์€ ์ ์šฉ ๊ฐ€๋Šฅ์„ฑ์„ ๊ฐ•์กฐํ•˜๊ธฐ ์œ„ํ•œ Attack Setting์— ๋Œ€ํ•ด์„œ ์„ค๋ช…ํ•œ๋‹ค.
    2. ๋‘๋ฒˆ์งธ๋กœ ์–ด๋–ป๊ฒŒ ์œˆ๋„์šฐ,๋ฆฌ๋ˆ…์Šค,๋“ฑ์˜ ๊ฐœ์ธ ์ปดํ“จํ„ฐ ๊ทธ๋ฆฌ๊ณ  ์•ˆ๋“œ๋กœ์ด๋“œ ๋ชจ๋ฐ”์ผํฐ, ํด๋ผ์šฐ๋“œ์—์„œ meltdown์ด mount๋  ์ˆ˜ ์žˆ๋Š”์ง€ ๋งํ•œ๋‹ค.
    3. ๋งˆ์ง€๋ง‰์œผ๋กœ meltdown ๊ตฌํ˜„์ด kernel memory๋ฅผ ๋น ๋ฅธ ์†๋„๋กœ dumpํ•˜๋Š” ๊ฒƒ์— ๋Œ€ํ•ด์„œ ๋งํ•œ๋‹ค.
  • Attack setting
    • ๊ฐœ์ธ์ปดํ“จํ„ฐ์™€ ๊ฐ€์ƒ ๋จธ์‹ ์€ ํด๋ผ์šฐ๋“œ์— ์žˆ๋‹ค๋Š” ๊ฐ€์ •
    • ๊ณต๊ฒฉ์ž๋Š” ์ž„์˜์˜ ๊ถŒํ•œ์ด ์—†๋Š” ์ฝ”๋“œ ์‹คํ–‰์„ ๊ฐ–๊ณ  ์žˆ๋‹ค๋Š” ๊ฐ€์ •(์ฆ‰, ๊ณต๊ฒฉ์ž๋Š” ์ผ๋ฐ˜ ์œ ์ €์˜ ๊ถŒํ•œ๋งŒํผ ์–ด๋–ค ์ฝ”๋“œ๋ฅผ ์‹คํ–‰ํ•  ์ˆ˜ ์žˆ๋‹ค)
    • ๊ณต๊ฒฉ์ž๋Š” ๋ฌผ๋ฆฌ ๋ฉ”๋ชจ๋ฆฌ ์ ‘๊ทผ์„ ํ•˜์ง€ ๋ชปํ•œ๋‹ค๋Š” ๊ฐ€์ •
    • ์‹œ์Šคํ…œ์€ ์ตœ์‹ ์ƒํƒœ์˜ ๋ณด์•ˆ(ASLR,KASLR,SMAP..)์˜ ์ƒํƒœ
    • ๋ฒ„๊ทธ๊ฐ€ ์—†๋Š” os์ด๊ณ , kernel์ฃผ์†Œ๋ฅผ ์ ‘๊ทผํ•˜๋Š” ๊ฒƒ์— ์ทจ์•ฝ์ ์ด ์—†๋Š” ์ƒํƒœ์ด์–ด์•ผํ•จ
    • ๊ณต๊ฒฉ์ž์˜ ์ตœ์ข… ๋ชฉํ‘œ๋Š” ์œ ์ €์˜ ๋ฐ์ดํ„ฐ(password,private key)๋“ฑ์„ ์ถ”์ถœํ•˜๊ณ ์ž ํ•จ

Attack Description



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